Storage Device and Data Control Method for Storage Error Control

ABSTRACT

A storage device includes a data storage medium and a control unit. The data storage medium includes a spare block pool including a plurality of spare blocks. Each spare block includes a plurality of data pages. The control unit is electrically coupled to the data storage medium. The control unit is configured to receive data from a host and to determine whether the data is sequential data according to a default policy. The data is written into at least two of the plurality of data pages in one of the plurality of spare blocks respectively. The control unit and a data storing method for the storage device are also provided.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of an application Ser.No. 15/396,784, filed on Jan. 02, 2017, and based upon and claims thebenefit of priority from the prior Taiwanese Patent Application No.105107810, filed Mar. 14, 2016, the entire contents of which areincorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to data storage technology, and moreparticularly to a storage device, a control unit thereof, and a datastoring method for storage device.

BACKGROUND OF THE INVENTION

In general, storage device is mainly constituted by a control unit and adata storage medium (for example, a flash memory). The data storagemedium includes a plurality of physical blocks, and each physical blockincludes a plurality of data pages. The control unit is electricallycoupled to the data storage medium and configured to perform data write,data read or data erase on the data pages in the physical blocks.

However, the storage device may have data integrity issues caused byfrequent data moving, defect in the manufacturing process and aging ofdata after long-term usage. Therefore, once data write is completed, thecontrol unit of the storage device may use error correcting code (ECC)to perform a correcting operation on the data stored in the storagedevice. However, the correcting capability of the error correcting codehas a limitation (e.g., 60 bits). Therefore, once the data stored in thedata pages has an error greater than 60 bits, the stored data may not becorrected by the error correcting code and an error correcting codeinvalid issue would happen, leading to loss of validity of the datastored in the storage device.

SUMMARY OF THE INVENTION

One objective of the present invention is to provide a storage device.When performing a data write operation, the storage device would make abackup of the written data. Therefore, once any one of the two pieces ofdata has an error correcting code invalid issue, the storage device mayselect and store the other piece of data not having the error correctingcode invalid issue. Or, if both of the two pieces of data have the errorcorrecting code invalid issue, the storage device may integrate the datapages of the two pieces of data to form one piece of data without theerror correcting code invalid issue. As a result, data loss is avoided.

Another objective of the present invention is to provide a control unitof a storage device. When performing a data write operation, the controlunit would make a backup of the written data. Therefore, once any one ofthe two pieces of data has an error correcting code invalid issue, thecontrol unit may select and store the other piece of data not having theerror correcting code invalid issue. Or, if both of the two pieces ofdata have the error correcting code invalid issue, the control unit mayintegrate the data pages of the two pieces of data to form one piece ofdata without the error correcting code invalid issue. As a result, dataloss is avoided.

Still another objective of the present invention is to provide a datastoring method for a storage device. When performing a data writeoperation, the data storing method would make a backup of the writtendata. Therefore, once any one of the two pieces of data has an errorcorrecting code invalid issue, the data storing method may select andstore the other piece of data not having the error correcting codeinvalid issue. Or, if both of the two pieces of data have the errorcorrecting code invalid issue, the data storing method may integrate thedata pages of the two pieces of data to form one piece of data withoutthe error correcting code invalid issue. As a result, data loss isavoided.

The present invention provides a storage device, which includes a datastorage medium and a control unit. The data storage medium includes aspare block pool. The spare block pool includes a plurality of spareblocks. Each one of the plurality of spare blocks includes a pluralityof data pages. The control unit is electrically coupled to the datastorage medium. The control unit is configured to receive data from ahost and to determine whether the data is sequential data according to adefault policy. The data is written into at least two of the pluralityof data pages in one of the plurality of spare blocks respectively.

The present invention further provides a control unit, which includes acontrol logic and a microprocessor. The control logic is electricallycoupled to a data storage medium. The data storage medium includes aspare block pool. The spare block pool is for storing a plurality ofspare blocks. Each one of the plurality of spare blocks includes aplurality of data pages. The microprocessor is electrically coupled tothe control logic. The microprocessor is configured to receive data froma host and determine whether the data is sequential data. If thedetermination is true, the microprocessor is configured to write thedata into at least two of the plurality of spare blocks via the controllogic respectively. If the determination is false, the microprocessor isconfigured to write the data into at least two of the plurality of datapages in one of the plurality of spare blocks via the control logicrespectively.

The present invention still further provides a data storing method for astorage device, which includes the steps of: receiving data from a host;determining whether the data is sequential data; if the determination istrue, writing the data into at least two spare blocks respectively,wherein the at least two spare blocks are selected from a plurality ofspare blocks of a spare block pool, and each one of the plurality ofspare blocks comprises a plurality of data pages; or if thedetermination is false, writing the data into at least two of theplurality of data pages in one of the plurality of spare blocks in thespare block pool respectively.

In summary, when performing a data write operation, the presentinvention would make a copy of the written data. Therefore, once any oneof the two pieces of data has an error correcting code invalid issue,the present invention may select and store the other piece of data nothaving the error correcting code invalid issue. Or, if both of the twopieces of data have the error correcting code invalid issue, the presentinvention may integrate the data pages of the two pieces of data to formone piece of data without the error correcting code invalid issue. As aresult, data loss is avoided.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages, objectives and features of the present invention willbecome apparent from the following description referring to the attacheddrawings.

FIG. 1 is a schematic circuit block view of a storage device inaccordance with an embodiment of the present invention; and

FIG. 2 is a flowchart of a data storing method for a storage device inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will now be described more specifically withreference to the following embodiments. It is to be noted that thefollowing descriptions of preferred embodiments of this invention arepresented herein for purpose of illustration and description only. It isnot intended to be exhaustive or to be limited to the precise formdisclosed.

FIG. 1 is a schematic circuit block view of a storage device inaccordance with an embodiment of the present invention. As shown in FIG.1, the storage device 100 of the present embodiment mainly includes acontrol unit 110 and a data storage medium 120. The data storage medium120 logically includes an in-use block pool 130 and a spare block pool140. The spare block pool 140 is for storing spare blocks not writtenwith any (valid) data, such as the spare blocks 141-K; wherein K is anatural number. Once a spare block is written and filled with data, thespare block is re-defined as an in-use block, such as the in-use blocks131-M, and moved to the in-use block pool 130; wherein M is a naturalnumber. When a garbage collection process is performed, the data in aplurality of related in-use blocks is written to a spare block. Then,after a data erase process is performed, the plurality of in-use blocksare re-defined as spare blocks and moved to the spare block pool 140;and the spare block with written data is re-defined as an in-use blockand moved to the in-use block pool 130. Therefore, it is understood thatboth of the spare blocks 141-K and the in-use blocks 131-M areessentially physical blocks and can be interchanged logically. That is,the logical amount of the in-use blocks can be adjusted according to auser's requirement. As shown in FIG. 1, each in-use block logicallyincludes a plurality of data pages such as the data pages P1, P2, P3,P4, . . . , and PN, wherein N is a natural number. In the presentembodiment, the data storage medium 120 is realized by a non-volatilerandom-access memory with longer data retention time, such as flashmemory, magnetoresistive random access memory (Magnetoresistive RAM),ferroelectric random access memory (Ferroelectric RAM), etc.

As shown in FIG. 1, the control unit 110 is electrically coupled to thedata storage medium 120 and configured to control an operation (e.g.,data access or erase) of the data storage medium 120. In the presentembodiment, the control unit 110 includes an interface logic 112, amicroprocessor 114 and a control logic 116. The microprocessor 114 iselectrically coupled to the interface logic 112, via which themicroprocessor 114 is configured to receive commands (e.g., writecommand, read command, erase command, etc.) or data from a host (e.g.,an electronic device such as computer, mobile phone or digital camerawith arithmetic function [not shown]). The microprocessor 114 is furtherelectrically coupled to the data storage medium 120 via the controllogic 116. The microprocessor 114 is further configured to perform dataaccess or data erase on the data storage medium 120 via the controllogic 116.

In the present embodiment, when receiving a write command and data froma host, the microprocessor 114 would first determine whether thereceived data is sequential data. Herein, the sequential data means thatthe logic block addresses (LBA) corresponding thereto are sequentiallycontinuous. In addition, the number of sequentially-continuous logicblock address for the determination of sequential data is notnecessarily set to two and may be set to other values according to auser's requirement. For example, if the number ofsequentially-continuous logic block address for the determination ofsequential data is set to four, the microprocessor 114 would onlydetermine the data with more than four sequentially-continuous logicblock addresses as sequential data; otherwise non-sequential data wouldbe determined. Then, the microprocessor 114 adopts a data storage meanfor the data storage medium 120 specific to the determination result ofthe received data.

When it is determined that the data from a host is not sequential data,the microprocessor 114 selects one spare block from the spare block pool140 via the control logic 116 and writes the data into two data pages ofthe selected spare block via the control logic 116, respectively. Forexample, the microprocessor 114 first selects the spare block 141 fromthe spare block pool 140 via the control logic 116, and then writes thereceived data into the data page P1 as well as a backup into the datapage P2 of the spare block 141. In other words, both of the receiveddata and the backup thereof are stored in the same spare block 141. Inone preferred embodiment, the data page P1 and the data page P2 are twoadjacent data pages, as illustrated in FIG. 1. However, the data page P1and the data page P2 are not necessarily adjacent to each other inanother embodiment; for example, the microprocessor 114 may use aspecific equation or a random number generator to select the two datapages, but the present invention is not limited thereto. In addition,the number of backup can be more than one. In one embodiment, forexample, the number of backup is two and the microprocessor 114 mayfurther write the received data (another backup) into the data page P3of the spare block 141. Similarly, the received data and the two backupsthereof are stored in the same spare block 141.

To comply with the management of wear leveling, the spare block 141having the least number of data erase or having the longest time sincethe last data erase may be selected among the spare blocks 141-K in thespare block pool 140.

Alternatively, when it is determined that the data from a host issequential data, the microprocessor 114 selects two spare blocks fromthe spare block pool 140 via the control logic 116 and writes the datainto the two selected spare blocks via the control logic 116,respectively. For example, the microprocessor 114 first selects thespare blocks 142, 143 from the spare block pool 140 via the controllogic 116, and then writes the received data into the data page P1 ofthe spare block 142 as well as a backup into the data page P1 of thespare block 143.

When the two selected spare blocks are written and filled with data(i.e., all the data pages thereof are written and filled with data), themicroprocessor 114 then starts a data verification process; that is, themicroprocessor 114 uses error correcting code to perform a correctingoperation on the data in each data page of the two spare blocks. Whenany one of the data pages in any spare block has an error correctingcode invalid issue, that spare block is determined as having an errorcorrecting code invalid issue. Then, the microprocessor 114 determineswhether to perform a data integration on the two spare blocks accordingto whether an error correcting code invalid issue is present. Inaddition, for specific purposes, the microprocessor 114 may initiatewrite of dummy data into the blank data page in a spare block, so as toallow the spare block written and filled with data to enter the dataverification process.

When the data verification process is performed and it is determinedthat both of the two selected spare blocks do not have an errorcorrecting code invalid issue or only one spare block has an errorcorrecting code invalid issue, then the microprocessor 114 re-definesthe spare block (or one of the spare blocks) not having the errorcorrecting code invalid issue as an in-use block and moves the in-useblock into the in-use block pool 130 via the control logic 116. Theremaining spare block is recycled; that is, the remaining spare block iserased and moved to the spare block pool 140.

Herein the microprocessor 114 selecting the spare blocks 142 and 143 istaken as an example. In this example, it is assumed that both of thespare blocks 142, 143 are written and filled with data and that thespare block 142 has an error correcting code invalid issue whereas thespare block 143 does not have so. Then, the microprocessor 114re-defines the spare block 143 as an in-use block and moves this in-useblock into the in-use block pool 130 via the control logic 116. Inaddition, the microprocessor 114 erases the data in the spare block 142and moves the spare block 142 into the spare block pool 140 via thecontrol logic 116.

Alternatively, when the data verification process is performed and it isdetermined that both of the two selected spare blocks have an errorcorrecting code invalid issue, then the microprocessor 114 furtherselects one spare block (referred to as the third spare block) from thespare block pool 140 and stores the data in the data pages not having anerror correcting code invalid issue in the two selected spare blocksthat are written and filled with data into the data pages in the thirdspare blocks. Then, when the third spare block is written and filledwith data and verified by the data verification process, themicroprocessor 114 defines the third spare block as an in-use block andmoves the third spare block into the in-use block pool 130. Then, thetwo selected spare blocks are erased and moved to the spare block pool140.

Herein the microprocessor 114 selecting the spare blocks 142 and 143 istaken as an example. In this example, it is assumed that both of thespare blocks 142, 143 are written and filled with data; the data pagesP1, PN in the spare block 142 have an error correcting code invalidissue; the data page P1, PN in the spare block 143 does not have anerror correcting code invalid issue; the data pages P2, PN-1 in thespare block 143 have an error correcting code invalid issue; and thedata page P2, PN-1 in the spare block 142 does not have an errorcorrecting code invalid issue. Then, the microprocessor 114 furtherselects one spare block (e.g., the spare block 144) from the spare blockpool 140 as the third spare block and stores the data in the data pagesP2-PN-1 of the spare block 142 and the data pages P1, PN of the sparepage 143, into the spare block 144. During the data verification processand after the data is written into the spare block 144, themicroprocessor 114 may further re-verify the data to make sure the datahas been correctly written into the spare block 144. If it is determinedthat the data page in the spare block 114 also has the error correctingcode invalid issue, the microprocessor 114 further selects one spareblock (e.g., the spare block 145) from the spare block pool 140 via thecontrol logic 116, refers the selected spare block 145 as the thirdspare block, and then repeats the aforementioned process. Then, when thethird spare block is written and filled with data and verified by thedata verification process, the microprocessor 114 defines the thirdspare block as an in-use block and moves the third spare block into thein-use block pool 130. In addition, the microprocessor 114 erases thedata of the spare blocks 142, 143 and moves the spare blocks 142, 143into the spare block pool 140 via the control logic 116.

A data storing method for a storage device can be developed according tothe above teachings. FIG. 2 is a flowchart of a data storing method fora storage device in accordance with an embodiment of the presentinvention. As shown in FIG. 2, the data storing method for a storagedevice of the present embodiment includes steps of: first, receivingdata from a host (step S201); then, determining whether the data issequential data (step S202); if yes, writing the data into at least twospare blocks respectively, wherein the at least two spare blocks areselected from a spare block pool and both include a plurality of datapages (step S203); alternatively, if no, writing the data into at leasttwo data pages of a spare block selected from the spare block poolrespectively (S204).

In summary, when performing a data write operation, the presentinvention would make a backup of the written data. Therefore, once anyone of these two data has an error correcting code invalid issue, thepresent invention may select and store another data not having the errorcorrecting code invalid issue g. Or, if both of these two data have theerror correcting code invalid issue, the present invention may integratethe pieces of these two data to form one data without the errorcorrecting code invalid issue. As a result, data loss is avoided.

While the invention has been described in terms of what is presentlyconsidered to be the most practical and preferred embodiments, it is tobe understood that the invention needs not be limited to the disclosedembodiments. On the contrary, it is intended to cover variousmodifications and similar arrangements included within the spirit andscope of the appended claims which are to be accorded with the broadestinterpretation so as to encompass all such modifications and similarstructures.

What is claimed is:
 1. A method of data programming for a storagedevice, comprising steps of: receiving a plurality of data from a host;programming the data into a group of spare block if a plurality oflogical block addresses of the data are sequential; and programming thedata into a spare block a plurality of times if the logical blockaddresses of the data are not sequential.
 2. The method of dataprogramming for a storage device according to claim 1, wherein the dataare programmed into the spare block sequentially.
 3. The method of dataprogramming for a storage device according to claim 1, wherein the dataare programmed into the spare block not in sequence.
 4. A method of dataverification for a storage device, comprising steps of: determiningwhether a spare block from a group of spare block does not have an errorcorrection code invalid issue; defining the spare block as an in-useblock and linking the rest spare block of the group of spare block intoa spare pool if the determination is true; and selecting a spare blockfrom the spare pool to store data not having the error correction codeinvalid issue from the group of spare block.